Contention-Aware Mapping and Scheduling Optimization for NoC-Based MPSoCs

Network-on-Chip (NoC) has emerged as an alternative interconnecting paradigm in the state-of-the-art multi-core architectures. Its capability of parallel data transfer over various paths increases the possibility of resource contention and causes network congestion. How to avoid contention, as well as to optimize performance and energy consumption becomes a great challenge for system designers. In this paper, we consider spatial and temporal aspects of communication to avoid contention. In spatial aspect, we propose to utilize overlapped communication paths to estimate the degree of contention, such that they can be minimized in mapping stage. In temporal aspect, we sequentialize data transfer with potential contention by introducing additional latency. To optimize the design concerns with the corresponding constraint model, we further provide an efficient algorithm to search for better solutions for the problem, which integrates a local search process into a genetic algorithm and applies various heuristics in initialization and evolution process. Experimentations from random and real-case benchmarks demonstrate the efficiency of our method in multi-objective optimization and the effectiveness of our techniques in avoiding network contention, while keeping performance and energy consumption optimized.