Finite state machine (FSM) is a computation model that consists of a finite set of states, a start state, an input alphabet, and a transition function that defines the next state and/or outputs based on the current state and input symbols. Finding an equivalent FSMwith minimal number of states is generally referred as state minimization or state reduction (SR) problem. State minimization is an effective approach in logic synthesis to optimize sequential circuit design in terms of area and power(Kam, 1997). The SR problem of FSM is NP-complete and can be treated as a special case of the Constraint Satisfaction Problem(CSP) where the transition function defines all the constraints that need to be satisfied. Interestingly, we observe that not all the constraints are required to obtain a given SR solution. Identifying the redundancy in the FSM will be useful in the following occasions. First, it helps to understand the nature of the NP-complete SR problem and to build FSM benchmarks to test the effectiveness of SR solvers. Second, the redundancy can be utilized to hide information and thus provide security protection to the FSM. Simulation results on real life FSMs reveal the existence of extremely rich redundancy.