Neural Networks in CMOS Manufacturing: Some Examples

Proceedings of the Artificial Intelligence and Manufacturing Research Planning Workshop, 1998

Volume

Proceedings of the Artificial Intelligence and Manufacturing Research Planning Workshop, 1998

Contents

The focus of this paper will be on two neural network models for plasma aided CMOS manufacturing. Both models were developed with strict statistical cross-validation and applied to real world applications. A plasma neural network gate etch controller has shown a 20% improvement in throughput in wafer processing by eliminating a set-up step, and has reduced the variance of thickness of an etched film by 40%. In a second example, a multistep system model was built that enabled us to Pareto rank the various processing steps and their impact on a yield metric. A similar model allows us to predict yield for the multistep process prior to completion of manufacturing. With these large scale system models we can essentially do feedback and feedforward control of a manufacturing line with engineers in the control loop. In summary we show the results for an on-line neural network controller and we show results for decision support tools for the engineering staff.