Motohide Otsubo, Satoru Fujita, Toru Yamanouchi
In the VLSI logic synthesis, high-performance CAD systems have various commands corresponding to various algorithms. These systems enable designers to synthesize the optimal circuit by repeatedly selecting and invoking the most appropriate-looking command. However they are hard for novice users to operate because it takes experience to select the command. In the past, the novices use a Simple Optimization Command (SOC) to automate command invocation. Although, it has the problem to maintain its heuristics up to date and lacks the automatic consideration of deadline time.
To cope with these problems, we have developed an intelligent command Control Shell (ICCS), which performs logic synthesis tasks by automatically selecting an executing different sequences of commands until it reaches the time limit unless it has already produced an adequate circuit.
ICCS uses statistical data as its knowledge, so we can update it quickly. By its time-constrained control, ICCS selects commands taking account of the time limit and can reach better circuit within the time. Especially using large-scale practical circuits, the ICCS resulted in circuits with 6% shorter delay in average, 30% shorter delay in best case than the circuits obtained by SOC