Design for Testability

Peng Wu

This paper presents an implemented system for modifying digital circuit designs to enhance testability. The key contributions of the work are: (1) setting design for testability in the context of test generation, (2) using failures during test generation to focus on testability problems, (3) indexing from these failures to a set of suggested circuit modifications. This approach does not add testability features to the portions of the circuit that a test generator can already handle, therefore, it promises to reduce the area and performance overhead necessary to achieve testability. While the system currently has only a small body of domain knowledge, it has demonstrated its ability to integrate different DFT techniques and to introduce only sharply focused modifications on a textbook microprocessor, an ability that is missing in previous DFT systems.


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